This disclosure is directed to electronic circuits and, more particularly, to methods and systems for interfacing and testing of integrated circuits.
The evolution of integrated circuits has led to electronic devices of ever increasing density and complexity. With these increased levels of integration, artisans within the IC industry have often confronted various compromises associated with manufacturability, test and/or functionality. On one hand, artisans may seek to design devices with a large number of interfacing links to assist more ready integration and functionality within particular system level applications. On the other hand, they may seek to reduce the size of the chip for reduced costs; which may therefore limit the physical real-estate and the number of pin/pads that may be formed for interfacing.
Also factoring into the various design considerations may be the need to assist ease of manufacturing and test. Accordingly, some typical methods of testing have been developed to facilitate testing by way of test vectors; wherein input vectors may be presented to a give portion of the integrated circuit while resulting vectors may be retrieved and analyzed for determining device functionality. For some of these procedures, a given chip may be designed with a plurality of input/output pads or pins dedicated to test. It may be understood, however, that such dedication of pads or pins to test may have an adverse impact the I/O bandwidth or functionality which might otherwise be desired for the integrated circuit.
Some methods of testing of integrated circuits may seek to increase the coverage or scope of testing, which may further contribute to device complexity—as may often be associated with certain flip-chip, chip-scale package and other high-density (e.g., fine pitch ball grid array FPGA) devices. In some cases, the manufactures incorporate circuits within these devices for performing built-in self tests and/or diagnostics. Results of such built-in self tests might then be made available for retrieval via a given number of dedicated test pads/pins.
Further facilitating integrated circuit testing, some within the industry have evolved boundary scan techniques and circuits of known tools available to assist with the routing and recovery of test vectors to/from various portions of an integrated circuit. One such form of boundary scan procedure, known to artisans in the industry as JTAG, may be understood to refer to a standard written by the Joint Test Action Group, and also similarly adopted by the IEEE in IEEE Standard 1149, for IEEE Standard Test Access Port and Boundary-Scan Architecture, which is incorporated herein by reference. Typically, the JTAG standard may be understood to define, in general, a 4-pin serial data transfer structure for accessing and controlling a standard test interface protocol and/or platform to various nodes of a digital circuit, which may also be know to assist with testing of circuitry within a chip.
To assist ease of manufacturing of the integrated circuits, artisans may strive to sustain avenues into these integrated circuits for supporting test. But despite some of the compelling needs for testing, some may find the interfacing needs for ordinary application of even more importance, especially where the devices may be understood to be designated for integration into higher level systems, as in the case of a given flip-chip device that is to be embedded with various other devices such as processors, buses, and/or network controllers and the like within a larger system. It may be understood, therefore, that some of these enhanced levels of integration may place a further premium on the limited number of pins/pads that may be available for interfacing such electrical devices.